199 Verification Engineer jobs in Malaysia

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• Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance and functionality through rigorous testing and simulation.
• Develop and execute design verification plans to ensure functional correctness and compliance with specifications.
• Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards.
• Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM).
• Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture.
• Define and implement functional coverage.
• Perform coverage analysis and identify testing gaps.
• Develop test plan and testcases from specification document.

Requirements:

• Possess at least 3 years experiences in USB/USB2.0/USB3.0
• Strong coding with Verilog and System Verilog.
• Good knowledge of design verification methodology UVM.
• Experiences with sequence creation, functional cover groups and assertion coding.
• Familiar with scripting language, such as Perl, C shell, Makefile, Ruby,Bash, TCL.
• Familiar with AMBA protocols i.e. AXI, AHB, APB etc.
• Understanding of low power design techniques (clock gating, power gating etc

Seniority level

• Seniority level Mid-Senior level

Employment type

• Employment type Full-time

Job function

• Industries IT Services and IT Consulting

Referrals increase your chances of interviewing at ThunderSoft by 2x

Sign in to set job alerts for “Design Verification Engineer” roles. Graduate Trainee - Silicon Design Engineer (Verification) Digital IC Design Engineer in Penang, Malaysia High Energy Efficiency Chip Verification Engineer Graduate Talent – FPGA IP Software Development Engineer

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Direct message the job poster from UST Malaysia

Hiring Top Semiconductor Engineers across APAC Region and Vietnam | Connecting Talents to Opportunities | Talents Strategist | Follow me for more Job…

Who we are:

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at

We are seeking a skilled and experienced Design Verification Engineer to join our dynamic team in Penang, Malaysia. The ideal candidate will play a pivotal role in ensuring the functional correctness, power efficiency, and protocol compliance of our cutting-edge semiconductor designs. This position is suited for individuals with a strong technical background in advanced verification methodologies and protocols.

Experience: 4+ years

Key Responsibilities:

• Develop and implement constrained-random verification environments using SystemVerilog and UVM .
• Write and execute test plans , testcases , scoreboards , monitors , and coverage models.
• Debug and analyze test failures to identify RTL or testbench issues.
• Collaborate closely with RTL designers, architecture, and firmware teams to ensure design correctness and coverage closure.
• Develop reusable verification components and contribute to the improvement of the verification infrastructure and methodology.
• Analyze functional and code coverage metrics; drive coverage closure.
• Participate in design and verification reviews and provide feedback on specifications and testability.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of experience in ASIC/SoC verification using SystemVerilog and UVM .
• Strong understanding of digital design and verification fundamentals.
• Experience with simulation tools (e.g., VCS , Questa , Incisive ) and waveform viewers (DVE , Verdi ).
• Proficiency in scripting languages (e.g., Python , Perl , Shell , TCL ) for automation.
• Strong debugging and problem-solving skills.
• Experience with version control systems (Git , Perforce ) and bug tracking tools.

Contact Ms. Anna - WhatsApp: +84 935059669

Email: anh.thivannguyen@ ust.com

Seniority level

• Seniority level Mid-Senior level

Employment type

• Employment type Full-time

Job function

• Industries Engineering Services and Semiconductor Manufacturing

Referrals increase your chances of interviewing at UST Malaysia by 2x

Sign in to set job alerts for “Design Verification Engineer” roles. Graduate Trainee - Silicon Design Engineer (Verification) SOC/FPGA Silicon Design Verification Engineer SOC/FPGA Silicon Design Verification Engineer Digital IC Design Engineer in Penang, Malaysia FPGA Pre Silicon Design Verification Engineer Senior R&D Test and Verification Engineer High Energy Efficiency Chip Verification Engineer

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Senior Verification Engineer page is loadedSenior Verification Engineer Apply locations Kuala Lumpur time type Full time posted on Posted 30+ Days Ago job requisition id R-620286

Change people’s lives and love what you do! Cochlear develops world-leading medical devices that help people hear. As a top 100 medical device company and market-leader in implantable hearing devices, more people choose a Cochlear-branded cochlear implant system than any other. Our employees tell us that the number one reason they enjoy working for Cochlear is the opportunity to make a difference to people’s lives.

The Senior Customer Software Verification and Validation Engineer is accountable for ensuring the output of complex projects are delivered in high-quality and on time to our customers by defining, executing, and reporting tests as required. The role has an important contribution to the product’s quality, reliability, and customer focus design experience as per approved functional and technical specifications within Cochlear Quality Management System framework.

This role reports to V&V Manager and the role works with V&V Lead, development teams, other V&V Engineers, Product Owners, Business Analyst, Software Delivery Managers, and Quality Engineers (when applicable). The senior V&V Engineer executes the V&V plans and partners with the development teams within a squad setup whilst ensuring the high-standard regulatory/quality compliance.

Accountabilities

• Understanding the functional and technical specifications in the context of Customer Software Products’ ecosystem and wider Cochlear Products’ ecosystem

• Creating test cases based on planning meetings, new feature/functions introduction, modification on existing feature/functions, and other relevant testing triggers

• Generating and maintaining input and output documentation for all verification and validation activities, including testable requirements assessment / designs input and V&V plan, and outputs from verification and validation activities, including documents and results

• Preparing frontend/backend/electronics/end-to-end test environment based on Test Coverage Review minutes and testing scope relevant to the target release

• Understanding the V&V test protocol and Test Coverage Review minutes to prepare the testing activities using required large arrays of test hardware and software combinations

• Ensure to execute test cases using correct hardware combinations required by test definition/Test Coverage Review minutes

• Producing reports that comply with Cochlear’s Quality Management System and specific regulatory standards (when applicable)

• Setting up correct test environment (manual/automated) as required by test definitions/Test Coverage Review minutes and escalate any potential issue related to the test hardware

• Training, mentorship, and guidance for other team members to ensure that objectives of the V&V team and the V&V requirements of project are met. Assume personal responsibility for the success of the team.

Key Incumbent requirements

• Tertiary qualification in relevant field of computing / engineering / science, or at least 4-6 years’ experience in a full lifecycle commercial software, delivering verification and validation for consumer facing devices in a successful product launch.

• Experience with test management tool and defect management tool

• Demonstrated experience in executing verification processes (frontend/backend/end-to-end), paying great attention to detail and meeting product quality standards.

• Experience in testing delivery within complex projects in compliance with quality/regulatory management system

• Solid understanding of test methodologies, Software Integration Testing and Software development life cycle / V-model

• Demonstrated ability to define test conditions for given requirements and designs

• Experience in functional testing

• Experience with electronics and electronic test equipment (Desirable)

Cochlear Malaysia provides shared services to support Cochlear’s global operations. The growing team of professionals in Malaysia provides critical support in areas such as IT infrastructure and applications, development and testing, business intelligence development and support, procurement, customer service, service and repairs and returned device analysis engineering.

If you feel that you have the skills and experience to be successful in this role and take on new challenges to build your career with Cochlear, please start your application by clicking the apply button below.

#CochlearCareers

Similar Jobs (2) Verification Engineer locations Kuala Lumpur time type Full time posted on Posted 30+ Days AgoCustomer Software Verification and Validation Engineer locations Kuala Lumpur time type Full time posted on Posted 22 Days Ago

Our growth is creating great opportunities!

Our team is expanding and we want to hire the most talented people we can. Continued success depends on it. So once you've had a chance to explore our current open positions, apply to the ones you feel suit you best and keep track of both your progress in the selection process, and new postings that might interest you!

We're the global leader in implantable hearing solutions. We have provided more than 600,000 implantable devices, helping people of all ages to lead full and active lives.

Our Mission

We help people hear and be heard. We empower people to connect with others and live a full life. We help transform the way people understand and treat hearing loss. We innovate and bring to market a range of implantable hearing solutions that deliver a lifetime of hearing outcomes.

#J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for data centers, artificial intelligence, PCs, gaming, and embedded systems. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance

THE ROLE:

We are looking for an adaptive, self-motivated design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team fosters continuous technical innovation and supports career development.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification. You are a team player with excellent communication skills and experience collaborating across different sites and time zones. You possess strong analytical and problem-solving skills, and are eager to learn and tackle new challenges.

KEY RESPONSIBILITIES:

• Develop and maintain tests for functional and performance verification at the SoC level.
• Build testbench components to support the next-generation SoC.
• Maintain and improve current test libraries and hardware emulation environments to enhance performance and debugging capabilities.
• Provide technical support to other teams.
• Verify SOC DFT features.
• Support silicon bring-up patterns and delivery.

PREFERRED EXPERIENCE:

• Proficiency in C/C++.
• Familiarity with SystemVerilog and modern verification libraries like UVM.
• Experience or background in DFT is a benefit.
• Verification experience is a plus.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

LOCATION:

Penang, Malaysia

#LI-JK1

#LI-Hybrid

Benefits offered are described at AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. We are an equal opportunity employer and consider all applicants without regard to legally protected characteristics. We encourage all qualified candidates to apply and will accommodate needs throughout the recruitment process.

#J-18808-Ljbffr

Design Verification Engineer page is loaded Design Verification Engineer Apply locations Penang 15 time type Full time posted on Posted Yesterday job requisition id R00273

Job Details:

Job Description:

We are looking for a talented design verification engineer to join our system engineering team.You will work with diverse multidisciplinary teams to drive key quality aspects of IP and System design.Our team operates in an agile and dynamic environment that requires hands-on involvement and close collaboration. Your main responsibilities will be focused on verifying IPs for video, vision, control systems, and diagnostics for functional safety. You will work on improving the quality and efficiency of existing test benches and the validation processes and methodologies, subsequently implementing those changes to advance best practices for hardware verification. Accountabilities include a full range of tasks within the verification cycle: Working with designers, architects, and security experts to capture and document verification specifications Improving verification environment and working closely with devops. Creation of a validation methodology by adopting industry standard verification techniques Creation and continuous improvement of testbench quality Developing and closing test coverage Owning reviews and testbench maintenance Drive the development of future verification strategy and infrastructure. Drive hardware coverage for different video protocol, including creating test plan, define testing strategy and driving execution Qualifications:

Essential skills and experience: 5+ years of design verification experience. Strong hands-on experience in functional verification of complex IP using System Verilog and UVM and developing reusable and scalable code. Strong scripting skills (UNIX shell scripting as well as e.g. TCL, Perl). Expert working knowledge of assertion-based verification. Hands-on RTL Debug capability and strong problem-solving skills. Experience with constrained-random verification including ownership of a suitably complex verification environment. Familiarity with tools and processes for developing and conducting all aspects of the verification process. Experience with continuous integration and automation systems (e.g. Jenkins) Strong communication skills and ability to work well as part of a team. Engineering mindset, dedicated and focused approach to problem analysis and solving. Being a self-starter and ability to estimate and plan your work Desirable skills and experience Knowledge of C/C++ based verification. Formal Verification experience. Experience with IP-XACT or similar descriptive formats Experience in media, video, imaging or display pipeline projects is desired Understanding of control systems and functional safety Technical leadership – managing, mentoring and coaching. Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

#J-18808-Ljbffr

1 day ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance and functionality through rigorous testing and simulation. Develop and execute design verification plans to ensure functional correctness and compliance with specifications. Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards. Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM). Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture. Define and implement functional coverage. Perform coverage analysis and identify testing gaps. Develop test plan and testcases from specification document. Requirements: Possess at least 3 years experiences in USB/USB2.0/USB3.0 Strong coding with Verilog and System Verilog. Good knowledge of design verification methodology UVM. Experiences with sequence creation, functional cover groups and assertion coding. Familiar with scripting language, such as Perl, C shell, Makefile, Ruby,Bash, TCL. Familiar with AMBA protocols i.e. AXI, AHB, APB etc. Understanding of low power design techniques (clock gating, power gating etc Seniority level

Seniority level Mid-Senior level Employment type

Employment type Full-time Job function

Industries IT Services and IT Consulting Referrals increase your chances of interviewing at ThunderSoft by 2x Sign in to set job alerts for “Design Verification Engineer” roles.

Graduate Trainee - Silicon Design Engineer (Verification)

Digital IC Design Engineer in Penang, Malaysia

High Energy Efficiency Chip Verification Engineer

Graduate Talent – FPGA IP Software Development Engineer

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

#J-18808-Ljbffr

Senior Verification Engineer page is loaded Senior Verification Engineer Apply locations Kuala Lumpur time type Full time posted on Posted 30+ Days Ago job requisition id R-620286 Change people’s lives and love what you do! Cochlear develops world-leading medical devices that help people hear. As a top 100 medical device company and market-leader in implantable hearing devices, more people choose a Cochlear-branded cochlear implant system than any other. Our employees tell us that the number one reason they enjoy working for Cochlear is the opportunity to make a difference to people’s lives. The

Senior

Customer Software Verification and Validation Engineer

is accountable for ensuring the output of complex projects are delivered in high-quality and on time to our customers by defining, executing, and reporting tests as required. The role has an important contribution to the product’s quality, reliability, and customer focus design experience as per approved functional and technical specifications within Cochlear Quality Management System framework. This role reports to V&V Manager and the role works with V&V Lead, development teams, other V&V Engineers, Product Owners, Business Analyst, Software Delivery Managers, and Quality Engineers (when applicable). The senior V&V Engineer executes the V&V plans and partners with the development teams within a squad setup whilst ensuring the high-standard regulatory/quality compliance. Accountabilities Understanding the functional and technical specifications in the context of Customer Software Products’ ecosystem and wider Cochlear Products’ ecosystem

Creating test cases based on planning meetings, new feature/functions introduction, modification on existing feature/functions, and other relevant testing triggers

Generating and maintaining input and output documentation for all verification and validation activities, including testable requirements assessment / designs input and V&V plan, and outputs from verification and validation activities, including documents and results

Preparing frontend/backend/electronics/end-to-end test environment based on Test Coverage Review minutes and testing scope relevant to the target release

Understanding the V&V test protocol and Test Coverage Review minutes to prepare the testing activities using required large arrays of test hardware and software combinations

Ensure to execute test cases using correct hardware combinations required by test definition/Test Coverage Review minutes

Producing reports that comply with Cochlear’s Quality Management System and specific regulatory standards (when applicable)

Setting up correct test environment (manual/automated) as required by test definitions/Test Coverage Review minutes and escalate any potential issue related to the test hardware

Training, mentorship, and guidance for other team members to ensure that objectives of the V&V team and the V&V requirements of project are met. Assume personal responsibility for the success of the team.

Key Incumbent requirements Tertiary qualification in relevant field of computing / engineering / science, or at least 4-6 years’ experience in a full lifecycle commercial software, delivering verification and validation for consumer facing devices in a successful product launch.

Experience with test management tool and defect management tool

Demonstrated experience in executing verification processes (frontend/backend/end-to-end), paying great attention to detail and meeting product quality standards.

Experience in testing delivery within complex projects in compliance with quality/regulatory management system

Solid understanding of test methodologies, Software Integration Testing and Software development life cycle / V-model

Demonstrated ability to define test conditions for given requirements and designs

Experience in functional testing

Experience with electronics and electronic test equipment (Desirable)

Cochlear Malaysia provides shared services to support Cochlear’s global operations. The growing team of professionals in Malaysia provides critical support in areas such as IT infrastructure and applications, development and testing, business intelligence development and support, procurement, customer service, service and repairs and returned device analysis engineering. If you feel that you have the skills and experience to be successful in this role and take on new challenges to build your career with Cochlear, please start your application by clicking the apply button below. #CochlearCareers Similar Jobs (2)

Verification Engineer locations Kuala Lumpur time type Full time posted on Posted 30+ Days Ago Customer Software Verification and Validation Engineer locations Kuala Lumpur time type Full time posted on Posted 22 Days Ago Our growth is creating great opportunities! Our team is expanding and we want to hire the most talented people we can. Continued success depends on it. So once you've had a chance to explore our current open positions, apply to the ones you feel suit you best and keep track of both your progress in the selection process, and new postings that might interest you! We're the global leader in implantable hearing solutions. We have provided more than 600,000 implantable devices, helping people of all ages to lead full and active lives. Our Mission

We help people hear and be heard. We empower people to connect with others and live a full life. We help transform the way people understand and treat hearing loss. We innovate and bring to market a range of implantable hearing solutions that deliver a lifetime of hearing outcomes.

#J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for data centers, artificial intelligence, PCs, gaming, and embedded systems. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance

THE ROLE:

We are looking for an adaptive, self-motivated design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team fosters continuous technical innovation and supports career development.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification. You are a team player with excellent communication skills and experience collaborating across different sites and time zones. You possess strong analytical and problem-solving skills, and are eager to learn and tackle new challenges.

KEY RESPONSIBILITIES:

Develop and maintain tests for functional and performance verification at the SoC level.

Build testbench components to support the next-generation SoC.

Maintain and improve current test libraries and hardware emulation environments to enhance performance and debugging capabilities.

Provide technical support to other teams.

Verify SOC DFT features.

Support silicon bring-up patterns and delivery.

PREFERRED EXPERIENCE:

Proficiency in C/C++.

Familiarity with SystemVerilog and modern verification libraries like UVM.

Experience or background in DFT is a benefit.

Verification experience is a plus.

ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

LOCATION:

Penang, Malaysia

#LI-JK1

#LI-Hybrid

Benefits offered are described at

AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. We are an equal opportunity employer and consider all applicants without regard to legally protected characteristics. We encourage all qualified candidates to apply and will accommodate needs throughout the recruitment process.

#J-18808-Ljbffr

Get AI-powered advice on this job and more exclusive features. Direct message the job poster from UST Malaysia Hiring Top Semiconductor Engineers across APAC Region and Vietnam | Connecting Talents to Opportunities | Talents Strategist | Follow me for more Job…

Who we are: At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at

We are seeking a skilled and experienced Design Verification Engineer to join our dynamic team in Penang, Malaysia. The ideal candidate will play a pivotal role in ensuring the functional correctness, power efficiency, and protocol compliance of our cutting-edge semiconductor designs. This position is suited for individuals with a strong technical background in advanced verification methodologies and protocols. Experience: 4+ years Key Responsibilities: Develop and implement constrained-random verification environments using

SystemVerilog

and

UVM . Write and execute

test plans ,

testcases ,

scoreboards ,

monitors , and

coverage

models. Debug and analyze test failures to identify RTL or testbench issues. Collaborate closely with RTL designers, architecture, and firmware teams to ensure design correctness and coverage closure. Develop reusable verification components and contribute to the improvement of the verification infrastructure and methodology. Analyze functional and code coverage metrics; drive coverage closure. Participate in design and verification reviews and provide feedback on specifications and testability. Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in ASIC/SoC verification using

SystemVerilog

and

UVM . Strong understanding of digital design and verification fundamentals. Experience with simulation tools (e.g.,

VCS ,

Questa ,

Incisive ) and waveform viewers ( DVE ,

Verdi ). Proficiency in scripting languages (e.g.,

Python ,

Perl ,

Shell ,

TCL ) for automation. Strong debugging and problem-solving skills. Experience with version control systems ( Git ,

Perforce ) and bug tracking tools. Contact

Ms. Anna - WhatsApp: +84 935059669 Email:

anh.thivannguyen@ ust.com Seniority level

Seniority level Mid-Senior level Employment type

Employment type Full-time Job function

Industries Engineering Services and Semiconductor Manufacturing Referrals increase your chances of interviewing at UST Malaysia by 2x Sign in to set job alerts for “Design Verification Engineer” roles.

Graduate Trainee - Silicon Design Engineer (Verification)

SOC/FPGA Silicon Design Verification Engineer

SOC/FPGA Silicon Design Verification Engineer

Digital IC Design Engineer in Penang, Malaysia

FPGA Pre Silicon Design Verification Engineer

Senior R&D Test and Verification Engineer

High Energy Efficiency Chip Verification Engineer

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

#J-18808-Ljbffr