63 Verification Designer jobs in Malaysia

1 day ago Be among the first 25 applicants

Get AI-powered advice on this job and more exclusive features.

• Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance and functionality through rigorous testing and simulation.
• Develop and execute design verification plans to ensure functional correctness and compliance with specifications.
• Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards.
• Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM).
• Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture.
• Define and implement functional coverage.
• Perform coverage analysis and identify testing gaps.
• Develop test plan and testcases from specification document.

Requirements:

• Possess at least 3 years experiences in USB/USB2.0/USB3.0
• Strong coding with Verilog and System Verilog.
• Good knowledge of design verification methodology UVM.
• Experiences with sequence creation, functional cover groups and assertion coding.
• Familiar with scripting language, such as Perl, C shell, Makefile, Ruby,Bash, TCL.
• Familiar with AMBA protocols i.e. AXI, AHB, APB etc.
• Understanding of low power design techniques (clock gating, power gating etc

• Seniority level Mid-Senior level

• Employment type Full-time

• Industries IT Services and IT Consulting

Referrals increase your chances of interviewing at ThunderSoft by 2x

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

Get AI-powered advice on this job and more exclusive features.

Direct message the job poster from UST Malaysia

Who we are:

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at

We are seeking a skilled and experienced Design Verification Engineer to join our dynamic team in Penang, Malaysia. The ideal candidate will play a pivotal role in ensuring the functional correctness, power efficiency, and protocol compliance of our cutting-edge semiconductor designs. This position is suited for individuals with a strong technical background in advanced verification methodologies and protocols.

Experience: 4+ years

Key Responsibilities:

• Develop and implement constrained-random verification environments using SystemVerilog and UVM .
• Write and execute test plans , testcases , scoreboards , monitors , and coverage models.
• Debug and analyze test failures to identify RTL or testbench issues.
• Collaborate closely with RTL designers, architecture, and firmware teams to ensure design correctness and coverage closure.
• Develop reusable verification components and contribute to the improvement of the verification infrastructure and methodology.
• Analyze functional and code coverage metrics; drive coverage closure.
• Participate in design and verification reviews and provide feedback on specifications and testability.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of experience in ASIC/SoC verification using SystemVerilog and UVM .
• Strong understanding of digital design and verification fundamentals.
• Experience with simulation tools (e.g., VCS , Questa , Incisive ) and waveform viewers (DVE , Verdi ).
• Proficiency in scripting languages (e.g., Python , Perl , Shell , TCL ) for automation.
• Strong debugging and problem-solving skills.
• Experience with version control systems (Git , Perforce ) and bug tracking tools.

Contact Ms. Anna - WhatsApp: +84 935059669

Email: anh.thivannguyen@ ust.com

• Seniority level Mid-Senior level

• Employment type Full-time

• Industries Engineering Services and Semiconductor Manufacturing

Referrals increase your chances of interviewing at UST Malaysia by 2x

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

Perform pre-Silicon verification on various IP blocks and full-chip FPGA/ASIC designs.

The job scope includes test plan definition, SystemVerilog/UVM test bench and content development, debugging, and running regression to deliver high-quality designs.

The candidate will work closely with the team and interact with product/IP architects, logic design engineers, DFX owners, and design automation engineers to ensure high-quality design validation.

This role is based in Penang.

Qualifications:

• BSEE/MSEE/PhD with at least 4 years of relevant experience
• Experience in functional verification, including test planning, test bench development, stimulus generation, reference model and assertion checker development, and functional coverage.
• Experience with modern verification techniques such as SystemVerilog OVM/UVM, assertion-based verification, constrained random verification methodologies .
• Familiar with IP protocols (e.g., HSST, Ethernet, PCIe, DDR), FPGA, and/or ARM architectures.
• Hands-on experience with various logic design and verification tools and flows from Cadence, Mentor Graphics, and/or Synopsys.

• Mid-Senior level

• Full-time

• Semiconductor Manufacturing

This job is active and accepting applications.

Overview:

We are looking for result-driven candidates who would thrive under a fast-pace working environment and having a strong desire to make an impact in their organization.

Job description:

• IC physical design of 6nm/4nm/3nm and below world leading advanced process chip, from RTL to GDS
• Block coordinator role for Synthesis/APR/PV tasks of more than 10 blocks, solving the critical issue and give the solution to block owners
• TOP role for the complicated hierarchical chip (more than 20 million instances plus 1000+ macros), doing floorplan, partition and assembly etc
• PD PM role to coordinate with Frontend and Signoff team about on time delivery of the SoC PD tasks, responsible for full chip PD schedule and tapeout

Job Requirements:

• Strong knowledge of IC design, leader role with tapeout experience is a must
• Strong knowledge of UNIX/LINUX env and capable of at least one of the following programming language: C/C++, Python, TCL, Perl
• Excellent communication and teamwork spirit, could coordinate with different teams to conquer all gating items, drive team to finish the assigned task on time with quality

PERSOLKELLY Singapore Pte Ltd • RCB No. 20007268E EA License No. 01C4394 • EA Registration No. R21103542 (Ling Kai Jin)

By sending us your personal data and CV, you are deemed to consent to PERSOLKELLY Singapore Pte Ltd and its affiliates to collect, use and disclose your personal data for account creation in GO and the purposes set out in the Privacy Policy . You acknowledge that you have read, understood, and agree with GO’s Terms of Use and the Privacy Policy. If you wish to withdraw your consent, please email us at Please feel free to contact us if you have any queries.

Join to apply for the Senior IC Design Verification Engineer role at Bitdeer (NASDAQ: BTDR)

1 month ago Be among the first 25 applicants

Join to apply for the Senior IC Design Verification Engineer role at Bitdeer (NASDAQ: BTDR)

Get AI-powered advice on this job and more exclusive features.

About Bitdeer

Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company also offers advanced cloud capabilities to customers with high demand for artificial intelligence. Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan.

About Bitdeer

Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company also offers advanced cloud capabilities to customers with high demand for artificial intelligence. Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan.

What You Will Be Responsible For

• Apply UVM (Universal Verification Methodology), SystemVerilog, Verilog, and SVA (SystemVerilog Assertions) languages in verification tasks
• Develop and implement state-of-the-art verification methodologies, including UVM, C/C++, co-simulation, system emulation, and mixed-mode simulation/emulation
• Contribute to projects requiring advanced verification tools such as Palladium Z1, HAPS, and Zebu platforms
• Collaborate effectively within a team, ensuring high-quality deliverables
  
  

• Possesses a Masters or Bachelors degree in Electrical Engineering or Computer Engineering
• At least 3 years of relevant experience
• Proficient in UVM, SystemVerilog, Verilog, and SVA languages
• Strong knowledge in protocols such as SPI, UART, and I2C
• Possesses knowledge of firmware development and in depth understanding of firmware development processes
• Excellent team player with strong communication skills.
• Highly driven and detail-oriented.
• Has experience working with advanced verification platforms like Palladium Z1, HAPS, or Zebu.
  
  

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.
  
  

• Seniority level Mid-Senior level

• Employment type Full-time

• Job function Engineering and Information Technology
• Industries Software Development

Referrals increase your chances of interviewing at Bitdeer (NASDAQ: BTDR) by 2x

Get notified about new Senior Design Verification Engineer jobs in Penang, Malaysia .

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.