65 Verification Designer jobs in Malaysia

Overview

Senior Talent Acquisition Specialist at UST Global

• Will be part of a team that handles Verification for complex IPs and closes the Verification to challenging milestones.
• IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation.
• Support in building verification infrastructure at the chip level as per the requirements.
• Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification.
• Working with the team and functional leads; some interaction with cross functional groups.

• Experience in digital IP verification with SV/UVM/Formal Verification or newer industry methodologies.
• Good understanding of ASIC verification concepts and techniques and Verilog/SystemVerilog and UVM.
• Proficiency in scripting languages such as Perl or Python is a plus; some database experience for IP technical information maintenance is also a plus.
• Over 4 years’ experience focusing on SV assertion/coverage/formal verification is a plus.
• Bachelor’s degree or higher in Electrical and Electronics Engineering or a related field.

• Associate

• Full-time

• Design

• Semiconductor Manufacturing

(Multiple headcounts available in different specializations)

• UVM & SV

Job Responsibilities:

• Be part of a team verifying complex IPs and driving them to closure against challenging milestones.
• Build verification environments and UVM/OVM testbenches based on chip requirements.
• Work across RTL, power-aware, and gate-level verification.

What we’re looking for:

• Bachelor’s degree (or higher) in Electrical/Electronic Engineering or related.
• 3–4+ years of hands‑on experience in digital IP verification using SV/UVM or similar methodologies.
• Solid knowledge of ASIC verification concepts.
• Bonus if you’ve dabbled in scripting (Perl/Python) or have database know‑how.
• Willing to relocate and work in Penang, Malaysia

• Seniority level Mid-Senior level

• Employment type Full-time

• Industries IT Services and IT Consulting

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Who we are:

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at

We are seeking a skilled and experienced Design Verification Engineer to join our dynamic team in Penang, Malaysia. The ideal candidate will play a pivotal role in ensuring the functional correctness, power efficiency, and protocol compliance of our cutting-edge semiconductor designs. This position is suited for individuals with a strong technical background in advanced verification methodologies and protocols.

Experience: 4+ years

• Develop and implement constrained-random verification environments using SystemVerilog and UVM .
• Write and execute test plans , testcases , scoreboards , monitors , and coverage models.
• Debug and analyze test failures to identify RTL or testbench issues.
• Collaborate closely with RTL designers, architecture, and firmware teams to ensure design correctness and coverage closure.
• Develop reusable verification components and contribute to the improvement of the verification infrastructure and methodology.
• Analyze functional and code coverage metrics; drive coverage closure.
• Participate in design and verification reviews and provide feedback on specifications and testability.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of experience in ASIC/SoC verification using SystemVerilog and UVM.
• Strong understanding of digital design and verification fundamentals.
• Experience with simulation tools (e.g., VCS, Questa, Incisive) and waveform viewers (DVE, Verdi).
• Proficiency in scripting languages (e.g., Python, Perl, Shell, TCL) for automation.
• Strong debugging and problem-solving skills.
• Experience with version control systems (Git, Perforce) and bug tracking tools.

Ms. Anna – WhatsApp:

Email:

• Mid-Senior level

• Full-time

• Engineering Services and Semiconductor Manufacturing

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Talent Acquisition @ UST | Talent Sourcing, Recruitment Strategies

• Will be part of a team that handles Verification for complex IP’s and close the Verification to the challenging milestones.
• IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation
• Support in building verification infrastructure at the chip level as per the requirements
• Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification
• Working with the team and functional leads; Some interaction with cross functional groups

• Have experience of digital IP verification with SV/UVM/Formal Verification or new methodology of the industry
• Good understanding of ASIC verification concepts and techniques and Verilog/System Verilog and UVM
• It’s a plus to be good at some script language, such as Perl, python. Or some database experience (for IP technical info maintain).
• It’s also a plus if have over 2 years’ experience focusing on SV assertion/coverage/formal verification.
• Bachelor’s degree or higher in Electrical and Electronics Engineering or related field
• 4-6 years of relevant experience

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Industries: Semiconductor Manufacturing

Location: Penang, Malaysia