365 Fpga Design jobs in Malaysia

SOC/FPGA Design Verification Engineering Lead/Manager page is loadedSOC/FPGA Design Verification Engineering Lead/Manager Apply locations Penang 15, Penang, Malaysia time type Full time posted on Posted 9 Days Ago job requisition id R00990Job Details: Job Description:

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.

As an SME verification engineering lead/manager you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness.

You will lead/manage a team of design verification engineers responsible for IP and SoC design verification. Deploys and manages leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. Works with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security-related testing through validation, hackathon reviews, and new validation techniques to improve security coverage. Executes security and security development lifecycle tasks per job role and schedule milestones. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Altera values, developing the capabilities of others, and ensuring a productive work environment.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.

• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.

• Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests.

• Collaborates and communicates with Architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.

• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.

• Maintains and improves existing functional verification infrastructure and methodology.

• Absorbs learning from post-silicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products

Qualifications:

Minimal Qualification:

* Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 15+ years of technical experience.

* Related technical experience should be in/with: Pre Silicon Validation/Verification, OVM/UVM, System Verilog, constrained random verification methodologies.

Preferred Qualification

* Lead/managed a team of engineers through multiple TO project cycles.

* Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.

* The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).

* Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.

* Scripting experience with TCL/PERL/Python etc.,

* Formal verification experience

* SME in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping

Job Type: RegularShift: Shift 1 (Malaysia)Primary Location: Penang 15, Penang, MalaysiaAdditional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Similar Jobs (5) SOC/FPGA Silicon Design Verification Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 9 Days AgoSOC/FPGA Silicon Design Verification Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 9 Days AgoStaff Design For Test Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 7 Days Ago

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SOC/FPGA Design Verification Engineering Lead/Manager

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Altera 1 day ago Be among the first 25 applicants Join to apply for the

SOC/FPGA Design Verification Engineering Lead/Manager

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Altera Job Description:

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Job Details

Job Description:

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.

As an SME verification engineering lead/manager you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness.

You will lead/manage a team of design verification engineers responsible for IP and SoC design verification. Deploys and manages leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. Works with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security-related testing through validation, hackathon reviews, and new validation techniques to improve security coverage. Executes security and security development lifecycle tasks per job role and schedule milestones. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Altera values, developing the capabilities of others, and ensuring a productive work environment.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with Architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products

Qualifications

Minimal Qualification:

Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 15+ years of technical experience. Related technical experience should be in/with: Pre Silicon Validation/Verification, OVM/UVM, System Verilog, constrained random verification methodologies.

Preferred Qualification

Lead/managed a team of engineers through multiple TO project cycles. Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Scripting experience with TCL/PERL/Python etc., Formal verification experience SME in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping

Job Type

Regular

Shift

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Seniority level

Seniority level Mid-Senior level Employment type

Employment type Full-time Job function

Job function Other Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at Altera by 2x Sign in to set job alerts for “SOC/FPGA Design Verification Engineering Lead/Manager” roles.

Parit Buntar, Perak, Malaysia 2 weeks ago Senior Manager Systems Design Engineering

MGR II R&D/PRODUCT DVL ENGINEERING-Mechanical Engineering

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SOC/FPGA Design Verification Engineering Lead/Manager page is loaded SOC/FPGA Design Verification Engineering Lead/Manager Apply locations Penang 15, Penang, Malaysia time type Full time posted on Posted 9 Days Ago job requisition id R00990

Job Details:

Job Description:

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. As an SME verification engineering lead/manager you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness. You will lead/manage a team of design verification engineers responsible for IP and SoC design verification. Deploys and manages leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. Works with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security-related testing through validation, hackathon reviews, and new validation techniques to improve security coverage. Executes security and security development lifecycle tasks per job role and schedule milestones. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Altera values, developing the capabilities of others, and ensuring a productive work environment. Performs functional logic verification of an integrated SoC to ensure design will meet specifications. • Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. • Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. • Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. • Collaborates and communicates with Architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. • Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. • Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. • Maintains and improves existing functional verification infrastructure and methodology. • Absorbs learning from post-silicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products Qualifications:

Minimal Qualification: * Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 15+ years of technical experience. * Related technical experience should be in/with: Pre Silicon Validation/Verification, OVM/UVM, System Verilog, constrained random verification methodologies. Preferred Qualification * Lead/managed a team of engineers through multiple TO project cycles. * Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. * The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). * Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. * Scripting experience with TCL/PERL/Python etc., * Formal verification experience * SME in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Similar Jobs (5)

SOC/FPGA Silicon Design Verification Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 9 Days Ago SOC/FPGA Silicon Design Verification Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 9 Days Ago Staff Design For Test Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 7 Days Ago

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WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

THE ROLE:

As an FPGA Platform Engineer, you will be responsible for designing and bringing up FPGA platforms for AMD SoC. You will collaborate closely with cross functional teams to define system requirements and design FPGA platforms with High-Speed IO. Your responsibilities will include:

• Defining and designing FPGA platforms with High-Speed IO
• Collaborating with cross functional teams to bring up FPGA platforms
• Testing and debugging FPGA platforms
• Providing technical support to customers

KEY RESPONSIBILITIES:

• Collaborate with cross functional groups for technical requirements and resolve technical challenges for FPGA solutions
• Design, implement, verify in simulation environment, and FPGA bring up for RTL Designs
• Debug FPGA Platform with AMD SoC and validate RTL Design in Hardware
• Gathers technical requirements during product definition and ensures implementation in platforms and documentation

PREFERRED EXPERIENCE:

• FPGA Design Experience with one High Speed IO Protocols (PCIe, Ethernet, CXL, DDR, or AXI)
• Proficiency with Verilog and/or System Verilog
• 3+ years of RTL Design experience for FPGA or ASIC
• Experience with FPGA Debug in Simulation and/or HW Bring up
• Experience with one of the scripting languages (Python, Perl, TCL, Bash, etc.)
• Strong Communication and problem solving skills
• Must be a self-starter, and able to independently drive tasks to completion

ACADEMIC CREDENTIALS:

• Bachelors or M asters degree in electrical or computer engineering.

LOCATION:

Penang, Malaysia

#LI-JL1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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Join to apply for the FPGA Circuit Design Engineer role at Altera

1 day ago Be among the first 25 applicants

Join to apply for the FPGA Circuit Design Engineer role at Altera

Get AI-powered advice on this job and more exclusive features.

• Designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip.
• Micro-architects and performs circuit and logic design, schematic entry, simulation, reliability verification, and verifies functionality to optimize FPGA circuits for power, performance, area, timing, and yield goals.
• Develops models and collaterals for FPGA circuits and IPs to integrate into FPGA hardware and software deliverables including circuit integration specifications, behavioral models, electrical rule checkers, design intent, and timing and power models.
• Collaboration with teams in different time zones to deliver best in class product
  
  

Job Details

Job Description:

• Designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip.
• Micro-architects and performs circuit and logic design, schematic entry, simulation, reliability verification, and verifies functionality to optimize FPGA circuits for power, performance, area, timing, and yield goals.
• Develops models and collaterals for FPGA circuits and IPs to integrate into FPGA hardware and software deliverables including circuit integration specifications, behavioral models, electrical rule checkers, design intent, and timing and power models.
• Collaboration with teams in different time zones to deliver best in class product
  
  

Qualifications

• Bachelor’s degree in electrical/Electronic Engineering or Computer Engineering is required .
• More than 5 years of experience in CMOS circuit design is preferred.
• Capable of reviewing the design within a broader team.
• Understand physics behind latest CMOS design process and layout dependent impact on performance , power and area.
  
  

Job Type

Regular

Shift

Shift 1 (India)

Primary Location:

Virtual - IND

Additional Locations:

Penang 16

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Seniority level

• Seniority level Mid-Senior level

Employment type

• Employment type Full-time

Job function

• Job function Engineering and Information Technology
• Industries Semiconductor Manufacturing

Referrals increase your chances of interviewing at Altera by 2x

Sign in to set job alerts for “Circuit Design Engineer” roles. Graduate Trainee - Silicon Design Engineer

Penang, Malaysia MYR200,000.00-MYR250,000.00 1 day ago

High Energy Efficiency Chip Design Engineer Graduate Trainee- Silicon Design Engineer (RTL) Manufacturing Design Engineer (based in Penang) Graduate Trainee - Silicon Design Engineer Graduate Trainee - Silicon Design Engineer (FEINT) Manufacturing Design Engineer (based in Penang) Memory Design Engineer (Schematic & Characterization)

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Join to apply for the

FPGA Circuit Design Engineer

role at

Altera 1 day ago Be among the first 25 applicants Join to apply for the

FPGA Circuit Design Engineer

role at

Altera Get AI-powered advice on this job and more exclusive features. Designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip. Micro-architects and performs circuit and logic design, schematic entry, simulation, reliability verification, and verifies functionality to optimize FPGA circuits for power, performance, area, timing, and yield goals. Develops models and collaterals for FPGA circuits and IPs to integrate into FPGA hardware and software deliverables including circuit integration specifications, behavioral models, electrical rule checkers, design intent, and timing and power models. Collaboration with teams in different time zones to deliver best in class product

Job Details

Job Description:

Designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip. Micro-architects and performs circuit and logic design, schematic entry, simulation, reliability verification, and verifies functionality to optimize FPGA circuits for power, performance, area, timing, and yield goals. Develops models and collaterals for FPGA circuits and IPs to integrate into FPGA hardware and software deliverables including circuit integration specifications, behavioral models, electrical rule checkers, design intent, and timing and power models. Collaboration with teams in different time zones to deliver best in class product

Qualifications

Bachelor’s degree in electrical/Electronic Engineering or Computer Engineering is required . More than 5 years of experience in CMOS circuit design is preferred. Capable of reviewing the design within a broader team. Understand physics behind latest CMOS design process and layout dependent impact on performance , power and area.

Job Type

Regular

Shift

Shift 1 (India)

Primary Location:

Virtual - IND

Additional Locations:

Penang 16

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Seniority level

Seniority level Mid-Senior level Employment type

Employment type Full-time Job function

Job function Engineering and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at Altera by 2x Sign in to set job alerts for “Circuit Design Engineer” roles.

Graduate Trainee - Silicon Design Engineer

Penang, Malaysia MYR200,000.00-MYR250,000.00 1 day ago High Energy Efficiency Chip Design Engineer

Graduate Trainee- Silicon Design Engineer (RTL)

Manufacturing Design Engineer (based in Penang)

Graduate Trainee - Silicon Design Engineer

Graduate Trainee - Silicon Design Engineer (FEINT)

Manufacturing Design Engineer (based in Penang)

Memory Design Engineer (Schematic & Characterization)

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

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WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_

THE ROLE: As an FPGA Platform Engineer, you will be responsible for designing and bringing up FPGA platforms for AMD SoC. You will collaborate closely with cross functional teams to define system requirements and design FPGA platforms with High-Speed IO. Your responsibilities will include: Defining and designing FPGA platforms with High-Speed IO Collaborating with cross functional teams to bring up FPGA platforms Testing and debugging FPGA platforms Providing technical support to customers KEY RESPONSIBILITIES: Collaborate with cross functional groups for technical requirements and resolve technical challenges for FPGA solutions Design, implement, verify in simulation environment, and FPGA bring up for RTL Designs Debug FPGA Platform with AMD SoC and validate RTL Design in Hardware Gathers technical requirements during product definition and ensures implementation in platforms and documentation PREFERRED EXPERIENCE: FPGA Design Experience with one High Speed IO Protocols (PCIe, Ethernet, CXL, DDR, or AXI) Proficiency with Verilog and/or System Verilog 3+ years of RTL Design experience for FPGA or ASIC Experience with FPGA Debug in Simulation and/or HW Bring up Experience with one of the scripting languages (Python, Perl, TCL, Bash, etc.) Strong Communication and problem solving skills Must be a self-starter, and able to independently drive tasks to completion ACADEMIC CREDENTIALS: Bachelors or

M

asters

degree in electrical or computer engineering. LOCATION: Penang, Malaysia #LI-JL1 #LI-Hybrid

Benefits offered are described:

AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

#J-18808-Ljbffr

SOC/FPGA Silicon Design Verification Engineer page is loadedSOC/FPGA Silicon Design Verification Engineer Apply locations Penang 15, Penang, Malaysia time type Full time posted on Posted 23 Days Ago job requisition id R00991Job Details: Job Description:

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.

As a verification engineer you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
• Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests.
• Collaborates and communicates with Architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
• Maintains and improves existing functional verification infrastructure and methodology.
• Absorbs learning from post-silicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products

Qualifications:

Minimal Qualification:

• Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience.
• Related technical experience should be in/with: Pre Silicon Validation/Verification.
• OVM/UVM, System Verilog, constrained random verification methodologies.

Preferred Qualification

• Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
• The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
• Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
• Scripting experience with TCL/PERL/Python etc.,
• Formal verification experience,
• SME experience in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping

Job Type: RegularShift: Shift 1 (Malaysia)Primary Location: Penang 15, Penang, MalaysiaAdditional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Similar Jobs (5) SOC/FPGA Silicon Design Verification Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 23 Days AgoDesign Verification Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 30+ Days AgoSOC/FPGA Design Verification Engineering Lead/Manager locations Penang 15, Penang, Malaysia time type Full time posted on Posted 23 Days Ago

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SOC/FPGA Silicon Design Verification Engineer page is loaded SOC/FPGA Silicon Design Verification Engineer Apply locations Penang 15, Penang, Malaysia time type Full time posted on Posted 23 Days Ago job requisition id R00991

Job Details:

Job Description:

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. As a verification engineer you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness. Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with Architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products Qualifications:

Minimal Qualification: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience. Related technical experience should be in/with: Pre Silicon Validation/Verification. OVM/UVM, System Verilog, constrained random verification methodologies. Preferred Qualification Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Scripting experience with TCL/PERL/Python etc., Formal verification experience, SME experience in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Similar Jobs (5)

SOC/FPGA Silicon Design Verification Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 23 Days Ago Design Verification Engineer locations Penang 15, Penang, Malaysia time type Full time posted on Posted 30+ Days Ago SOC/FPGA Design Verification Engineering Lead/Manager locations Penang 15, Penang, Malaysia time type Full time posted on Posted 23 Days Ago

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